Quantum Computing Scalability Conference 2025
LOCATION
Keble College, Oxford, UK
WHEN
2–4 April 2025
James Wills
QUANTUM ENGINEER
James completed his PhD in Physics at the University of Oxford, in the group of Peter Leek. He worked on the design, simulation, and measurement of novel coaxial qubits, specialising in multi-mode coaxial transmons for quantum computing and sensing applications. He joins OQC as a Quantum Engineer, working in the Quantum Research and Development team.
EVENT DETAILS
The NQCC’s Quantum Computing Scalability Conference is dedicated to tackling the key scalability issues across quantum platforms, from engineering challenges to advances in quantum physics. The conference brings together experts from diverse quantum computing fields, fostering cross-disciplinary insights and enabling honest assessments of scalability.
This April, we will be attending the Quantum Computing Scalability Conference 2025 and will be speaking on our latest technology advancements in hardware efficient quantum error-correction.
SESSION DETAILS
Hardware-efficient erasure error-detection in superconducting qubits
Date: Thursday 3rd April 2025, 11:30am
Speaker: Dr James Wills | Senior Quantum Engineer
Quantum error correction (QEC) demonstrations have shown encoding logical qubits can result in error-rates lower than those of the constituent physical qubits, provided the physical error rates are below thresholds. Increasing scale of devices whilst maintaining the high performance required for QEC poses a significant challenge to many architectures, and efficient encodings that alleviate these requirements are an active area of research.
Erasure error-detection consists of a qubit encoding that enables detectable leakage errors. In superconducting qubits, energy relaxation is a significant source of error, and it has been demonstrated that dual-rail encoding is able to convert this loss to erasure errors. QEC architectures utilising erasure error detection showing more readily accessible sub-threshold regimes have the potential to profoundly reduce hardware overheads required for algorithmically relevant error-rates. In addition, the ability to detect errors has utility for near-term algorithm improvement and early fault-tolerance applications.
Here we present a dual-rail encoding within a superconducting multimode qubit. We demonstrate the utility of the architecture as a quantum memory, showing logical error rates an order of magnitude lower than the physical error rates. Finally, we discuss how the unique sensitivities of the error-detected subspace can be used for investigations into the fundamentals of noise and decoherence in superconducting circuits.
