The challenges in readout of quantum information

Readout is the process in which qubits are measured or their state determined after quantum computation has occurred. The states of qubits are read using resonators which are coupled to the qubit. During readout however, a mechanism, known as the Purcell effect, is encountered in which qubit excitations decay directly into the readout channels. This mechanism must be controlled in a scalable way for fault-tolerant quantum computing to be achieved. While there are multiple ways to manage the Purcell effect and improve Purcell protection, many of the existing readout techniques in superconducting circuits lengthen the qubit readout time introducing a compromise between measurement speed and qubit coherence. 

Purcell filtering has become a widespread tool used to protect qubits from unwanted radiative relaxation through readout channels and to enable fast readout, thereby improving the trade-off imposed by the Purcell effect. While mitigating the Purcell effect to a high degree however, the footprint of the filters created are often larger than the qubit itself and lead to an increase in the size of the quantum processor. This in turn creates a new challenge to address with many current solutions requiring additional fabrication and packaging processes which often increase the complexity of the quantum processor manufacturing.  Using and improving Purcell filters to extend the lifetime of superconducting qubits is therefore an ever-present challenge in scaling quantum computing platforms.

OQC’s latest research in Purcell filters

While most superconducting quantum processors interface with printed circuit board (PCB) packaging for signal delivery, to-date there has been no reported work using Purcell filters integrated into such packaging. In our latest preprint, released on arXiv, our Quantum Science & Exploratory Research team present the development of novel Purcell filters integrated within a multilayer printed circuit board for superconducting quantum circuits. 

The integrated Purcell filter in the presented work is a means of countering the Purcell decay effect within qubits by limiting the photons that can decay through the resonator readout line. The proposed design achieves this by employing a novel method in which a bandpass filter is embedded within a multiplexing circuit using conventional PCB-based multilayer technology and an antenna-like design. 

The design splits a superconducting quantum processor into layers; containing qubits, resonators, filters, control and readout (Figure.1). The PCB stack consists of 3 layers where the filter is the middle layer, taking the form of a triangular-shaped, coplanar patch antenna with an out-of-plane feedline. The shape is chosen to maximise the coverage of multiple qubits while maintaining symmetry for tiling, whilst its middle layer position  protects any neighbouring filters from crosstalk.

Simulation and modelling

In the undertaken research, the design is simulated, manufactured and measured at cryogenic conditions with a 35-qubit chip. The filters are designed to have a wide bandpass response at the readout frequency of 10 GHz, and a 3 dB bandwidth of 0.88 GHz, meaning that any signals falling within this band are passed through the filter, while frequencies outside of this band are blocked. Through this process we enable frequency-multiplexed qubit state readout enabling support up to 9 readout channels.

Benefits to this novel approach

The results of this work carried out demonstrates that all qubits can be read using this PCB-based technology and shows a clear increase in the lifetime of the qubits. The off-chip design removes all filter components from the qubit substrate itself, enhancing device modularity and packaging reusability. With each filter able to couple to nine readout resonators simultaneously, multiplexed readout is also enabled.

The 3D design does not increase the physical footprint of the device, as it fits entirely within the footprint of the qubit layout itself. This enables a filter and signal layout which can be easily tileable and scalable for a larger number of qubit chips without increasing the complexity of the quantum processor manufacturing, a necessity as quantum computing scales towards fault-tolerant quantum compute.

Read the pre-print on arXiv: https://arxiv.org/abs/2602.24003